The semiconductor industry is poised for a big leap forward in chip design productivity. This could be a turning point
Fitting over 50 billion transistors onto a chip the size of a fingernail that is 150 square millimeters is an insanely intricate task that boggles the mind. Chip floor-planning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research, chip floor-planning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. However, a breakthrough is now transforming the semiconductor manufacturing industry. Companies are claiming that machine learning can automate the entire design process if the training model is fed with design goals only.
The industry is poised for a big leap forward in chip design productivity. Engineering teams now have access to massive compute power, either on-premises or using cloud resources, while machine learning has made significant progress, and is now ready and available for electronic design automation purposes. Both these technologies have enabled the next revolution in chip design – automated, machine learning-driven flow optimization.
A titanic challenge of design, space & optimization
It’s a titanic scale challenge of design, space, and optimization to cram so much into a nano-scale space that is one-eightieth the thickness of human hair. Today’s chips require more functionality but shrinking sizes, making chip design more and more complex. To meet the increasing market demand, engineering teams at leading semiconductor companies are using machine learning to optimize and automate design flows.
The smaller the chip (now at 2 nanometres) the faster, and more energy-efficient it is. IBM claimed that its 2 nm (nanometre) chips could quadruple cell phone battery life, speed up laptop functions, and slash the carbon footprint of data centers that would eventually run servers on the smaller chip nodes. Semiconductor manufacturers are, therefore, turning to artificial intelligence (AI) to solve the design and space optimization challenge.
Samsung leads in AI-designed chip use
Leading this space is the South Korean transnational, Samsung, which has become the first company to use AI in the process of designing its most advanced chips. Samsung is using AI features in new software from Synopsys, a leading chip design software firm contracted by many companies.
Synopsys ushered in a new era of the breakthrough chip design in early 2020 to deliver better, faster, and cheaper semiconductors. As the industry’s first autonomous AI application for chip design, DSO.ai searches for optimization targets in very large solution spaces of chip design, utilizing reinforcement learning to enhance power, performance, and area. By massively scaling exploration of design workflow options while automating less consequential decisions, the technology drives higher engineering productivity while swiftly delivering results that were not possible earlier.
Samsung has started using Synopsys design technology for its Exynos chips used in smartphones, including its own branded handsets, as well as other gadgets. The company unveiled its newest smartphone, a foldable device called the Galaxy Z Fold3, last month.
Google promises to cut design from months to six hours
Last year in June, Google published a research paper on its AI-based approach to designing the floor-plan – crunching months of rigorous human effort in just six hours using reinforcement learning. The approach, which lets a machine learn from experience and experimentation, has been key to some major advances in AI.
The search engine behemoth’s research team presented “…a deep reinforcement learning approach to chip floor-planning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance, and chip area. To achieve this, we pose chip floor-planning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip…Our method generates manufacturable chip floorplans in under 6 hours, compared to the strongest baseline, which requires months of intense effort by human experts.”
Nvidia testing design simulation
One of the world’s leading chip design and manufacturing company, Nvidia, is also testing how reinforcement learning can help arrange components on a chip and how to wire them together. The company’s scientists are exploring different chip designs in simulation, training a large artificial neural network to recognize which decisions ultimately produce a high-performing chip.
MIT R&D creates 2X energy-efficient chips
An MIT research team is also working on automatic transistor sizing using AI. Automatic transistor sizing is expected to sharply reduce manual effort in designing chips. Currently, designers first need to analyze the topology and derive equations for the performance metrics. Based on all the equations, the initial sizes are calculated. Then, a large number of simulations for parameter fine-tuning are performed to meet the performance specifications. The whole process can be highly labor-intensive and time-consuming owing to large design space, slow simulation tools, and sophisticated trade-offs between different performance metrics.
Inspired by the transfer learning ability of Reinforcement Learning (RL), MIT scientists are first training a RL agent on one circuit and then applying the same agent to size new circuits or the same circuit in new technology nodes. This helps reduce the simulation cost without designing from scratch. The AI tool produced circuit designs that were 2.3 times more energy-efficient while generating one-fifth as much interference as the ones designed by human engineers.
Specify the design goals, machine learning will do the rest
Cadence, a California-based computational software company has launched Cerebrus™ Intelligent Chip Explorer –a machine learning-driven, automated approach to chip design flow optimization. The company’s marketing material claims that engineers need only to specify the design goals, while Cerebrus will intelligently optimize the process to meet these power, performance, and area (PPA) goals in a completely automated way.“It is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems,” the company claims.
To enable the semiconductor industry to continue growing, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in machine learning computer science, the next chip design automation revolution is now possible. As the world grapples with severe semiconductor supply chain disruptions, automating the chip design process is promising to revolutionize the industry.
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